xc2s15-5tqg144c DataSheet
DATASHEET
xc2s15-5tqg144c 描述
xc2s15-5tqg144c 特点
The XC2S15-5TQG144C EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The XC2S15-5TQG144C is offered with two choices of temperature ranges, 0C to 70C (JL suffix) and C 40C to 85C (JE suffix). See Table 1.
xc2s15-5tqg144c 应用
n Internal comparator with pin programmable 2˚C or 10˚C hysteresis n No external components required n Open Drain or push-pull digital output; supports CMOS logic levels n Internal temperature sensor with VTEMP output pin n VTEMP output allows after-assembly system testing n Internal voltage reference and DAC for trip-point setting n Currently available in 5-pin SOT-23 plastic package n Excellent power supply noise rejection
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
17911
via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
4838
The BRT (Bias Resistor Transistor) contains
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
17079
3.1 KSO0~7 These pins are direct output from the
11091
n Internal Start-up Bias Regulator n 3A Compound
11204
IOAPIC clock output. (14.318 MHz) Poweredby VDDL