xc9572xl-10vqg44c DataSheet
DATASHEET
xc9572xl-10vqg44c 描述
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.
xc9572xl-10vqg44c 特点
Drain-to-Source Breakdown Voltage Gate Threshold Voltage Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Zero Gate Voltage Drain Current Static Drain-to-Source On-State Resistance (TO-39) Static Drain-to-Source On-State Resistance (SMD-0.5) Diode Forward Voltage
xc9572xl-10vqg44c 应用
Power Supply Input. The VDD range for the XC9572XL-10VQG44C is from +2.5V to +5.25V. Analog Ground. Ground reference point for all circuitry on the XC9572XL-10VQG44C. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the XC9572XL-10VQG44C´s conversion process. Data Out. Logic Output. The conversion result from the XC9572XL-10VQG44C is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the XC9572XL-10VQG44C consists of 4 leading zeros followed by 16 bits of conversion data which is provided MSB first. This will be followed by 4 trailing zeroes if CS is held low for a total of 24 SCLK cycles. See serial Interface section. Chip Select. Active low logic input. This input provides the dual function of initiating con- versions on the XC9572XL-10VQG44C and framing the serial data transfer. No Connect. This pin should be left unconnected.
相关型号
型号
数量
厂商
批号
描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
11466
High Power Switching Regulator Controller for DDR
10817
The internal circuit is composed of 2 stages inc
18287
The Edge646 driver supports three distinct program
19657
• True dual-ported memory cells which allow
6160
These Schottky barrier diodes are designed
7530
These data selectors/multiplexers contain invert
11204
IOAPIC clock output. (14.318 MHz) Poweredby VDDL
7372
pin signalised an interrupt (logic 0). However, if
14842
drivers to drive either 3.3V or 2.5V output level
18994
The ispLSI 5000VE encompasses the innovative fea-
16794
11+
II, the maximum input current at maximum input vo
8886
The mounting area was reduced by mak- ing the tw
18416
Power supply voltage VCCs = 2.7 V~3.6 V &
17046
I Dual-Mode Pin. Cascaded C The first device in th
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma