xc2s50-5pqg208c DataSheet
DATASHEET
xc2s50-5pqg208c 描述
via an RF or an infrared transmission medium upon receipt of a trigger signal. The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12A further enhances the ap- plication flexibility of the 212 series of encoders. The HT12A additionally provides a 38kHz car- rier for infrared systems.
xc2s50-5pqg208c 特点
The Hynix XC2S50-5PQG208C Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
xc2s50-5pqg208c 应用
Up to 2 Gsps Sampling Rate Power Consumption: 4.6 W 500 mVpp Differential 100 Ω or Single-ended 50 Ω (2 %) Analog Inputs Differential 100 Ω or Single-ended 50 Ω Clock Inputs ECL or LVDS Output Compatibility 50 Ω Differential Outputs with Common Mode not Dependent on Temperature ADC Gain Adjust Sampling Delay Adjust Offset Control Capability Data Ready Output with Asynchronous Reset Out-of-range Output Bit Selectable Decimation by 32 Functions Gray or Binary Selectable Output Data; NRZ Output Mode Pattern Generator Output (for Acquisition System Monitoring) Radiation Tolerance Oriented Design (More Than 100 Krad (Si) Expected) CBGA 152 Cavity Down Hermetic Package CBGA Package Evaluation Board TSEV83102G0BGL Companion Device: DMUX 8-/10-bit 1:4/1:8 2 Gsps TS81102G0
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10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
4950
Note 2: The maximum power dissipation is dictated
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
3275
Continuous Drain Current, VGS @ 10V Continuous D
7426
Drive Up To 15 LSTTL Loads Low Power Consumption,
13759
The A-to-B enable (CEAB) input must be low in ord
8886
The mounting area was reduced by mak- ing the tw
18416
Power supply voltage VCCs = 2.7 V~3.6 V &
17046
I Dual-Mode Pin. Cascaded C The first device in th