xc5vlx110t-1ffg1136c DataSheet
DATASHEET
xc5vlx110t-1ffg1136c 描述
Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380D/CY7C1382D operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
xc5vlx110t-1ffg1136c 特点
The XC5VLX110T-1FFG1136C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap around when incremented sufficiently. A HIGH input on
xc5vlx110t-1ffg1136c 应用
OUTPUT TRANSISTOR Collector-emitter Voltage BVCEO SFH600-0,1,2,3,4 SFH601-1,2,3,4,5 SFH609-1,2,3,4,5 Collector-base Voltage BVCBO SFH600-0,1,2,3,4 SFH601-1,2,3,4,5 SFH609-1,2,3,4,5 Emitter-collector Voltage BVECO Power Dissipation
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询价
10241
11+
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NOTES: 1. Stresses greater than those listed und