Z0107NA1AA2 DataSheet
DATASHEET
Z0107NA1AA2 描述
The floating-point register file is made up of thirty-two 64-bit regis- ters. With the LDC1 and SDC1 instructions the floating-point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every cycle.
Z0107NA1AA2 特点
The Z0107NA1AA2CMAX3183 are EIA/TIA-232 and V.28/ V.24 communications receivers that convert RS-232 signals to CMOS logic levels. The devices operate on a supply voltage of +3V to +5.5V and have a 1.5Mbps data rate capability. They achieve a 0.5µA typical sup- ply current. The Z0107NA1AA2/MAX3182 have a receiver enable control (EN), while the MAX3181/MAX3183 con- tain a signal invalid output (INVALID). The Z0107NA1AA2/ MAX3181 invert the ROUT signal relative to RIN. The MAX3182/MAX3183 are not inverted. The devices come in SOT23-5 packages.
Z0107NA1AA2 应用
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