XC2S50-5TQG144C DataSheet
DATASHEET
XC2S50-5TQG144C 描述
The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the desiralizer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The users system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted.
XC2S50-5TQG144C 特点
• Other features • Internal oscillator circuit as clock source • INIT is prepared as a reset terminal. • Watchdog timer reset. Software reset. • Low power consumption modes supported: Stop mode and Sleep mode • Gear function • Built-in time base timer • Package : LQFP-144, 0.5 mm pitch, 20 mm 20 mm • CMOS technology (0.25 µm) • Supply voltage: Dual power supplies at 3.3 V 0.3 V, 2.5 V 0.2 V
XC2S50-5TQG144C 应用
If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual per- channel programming on the Connect Memory High bits.
相关型号
型号
数量
厂商
批号
描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
4950
Note 2: The maximum power dissipation is dictated
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
3275
Continuous Drain Current, VGS @ 10V Continuous D
7426
Drive Up To 15 LSTTL Loads Low Power Consumption,
11466
High Power Switching Regulator Controller for DDR
4838
The BRT (Bias Resistor Transistor) contains
4950
Note 2: The maximum power dissipation is dictated
17911
via an RF or an infrared transmission medium upo
13759
The A-to-B enable (CEAB) input must be low in ord