XC2S200-5PQG208C DataSheet
DATASHEET
XC2S200-5PQG208C 描述
The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminates these individual components by integrating them into a single device. In the MUN5111DW1T1 series, two BRT devices are housed in the SOT−363 package which is ideal for low−power surface mount applications where board space is at a premium.
XC2S200-5PQG208C 特点
The top circuit provides a dynamically variable DC out- put voltage in the +0.4V to +3.4V range and provides up to 600mA as configured. A XC2S200-5PQG208C in a 10-pin µXC2S200-5PQG208CAX package is used for this circuit. To obtain up to +3.4V at the output, +3.6V to +5.5V must be fed to the input; 50Ω terminated BNC connectors are provided for the SYNC and REF signal pins that synchronize the cir- cuit to an external sine-wave source and adjust the out- put voltage with an external reference source, (for eval- uating the XC2S200-5PQG208CX and XC2S200-5PQG208CY) respectively. The bottom circuit supplies a +1.5V output at up to 600mA as configured. A XC2S200-5PQG208CAX1821 in a 10-pin µXC2S200-5PQG208CAX package is used for this circuit. A PC board pad is pro- vided for the SYNC signal, which synchronizes the cir- cuit to an external sine-wave source (for evaluating the XC2S200-5PQG208CAX1821X). The XC2S200-5PQG208C EV kit provides two jumper-selectable operational modes, Normal and Forced PWXC2S200-5PQG208C. In Normal mode, the circuit operates in Pulse Skip mode for light loads and PWXC2S200-5PQG208C mode for heavy loads. In Forced PWXC2S200-5PQG208C mode, the circuit always operates in PWXC2S200-5PQG208C mode for all loads.
XC2S200-5PQG208C 应用
The XC2S200-5PQG208C family of FPGAs offers four devices at the low end of the XC4000 family complexity range. XC2S200-5PQG208C differs from XC4000 in four areas: fewer routing resources, fewer wide-edge decoders, higher output sink current, and improved output slew-rate control.
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
17911
via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
3275
Continuous Drain Current, VGS @ 10V Continuous D
4950
Note 2: The maximum power dissipation is dictated
17911
via an RF or an infrared transmission medium upo
13759
The A-to-B enable (CEAB) input must be low in ord