XC3S100E-4TQG144C DataSheet
DATASHEET
XC3S100E-4TQG144C 描述
Note 2: The maximum power dissipation is dictated by TJMAX, JA, and the ambient temperature TA and must be derated at elevated temperatures. The maximum allowable power dissipation is PDMAX = (TJMAX − TA)/JA. For the LM4924, TJMAX = 150˚C. For the JAs, please see the Application Information section or the Absolute Maximum Ratings section.
XC3S100E-4TQG144C 特点
Organization . . . 4 194 304 1 Single 5 V Power Supply, for XC3S100E-4TQG144C / P ( 10% Tolerance) Single 3.3 V Power Supply, for XC3S100E-4TQG144C / P ( 10% Tolerance) Low Power Dissipation ( XC3S100E-4TQG144CP only) C 200-µA CMOS Standby C 200-µA Self Refresh C 300-µA Extended-Refresh Battery Backup Performance Ranges:
XC3S100E-4TQG144C 应用
Four channels of EMI filtering with ESD protection Greater than 30dB of attenuation from 800MHz to 3GHz 15kV ESD protection (IEC 61000-4-2, contact discharge) 30kV ESD protection (HBM) 8-lead TDFN package (2mm x 2mm), 0.5mm pitch Lead-free version available
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描述
询价
10241
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PARAMETER Reference Voltage Section Fb Voltage
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The floating-point register file is made u
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A high on the MASTER RESET (MR) sets all the cont
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Wiper position programming defaults to midscale a
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The CS5381 uses a 5th-order, multi-bit delta-sigma
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The mounting area was reduced by mak- ing the tw
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The A-to-B enable (CEAB) input must be low in ord
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Output, Pin 14, is suitable for controlling a pow
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The challenge for an integrated clock-recovery cir
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Continuous Drain Current, VGS @ 10V Continuous D
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Drive Up To 15 LSTTL Loads Low Power Consumption,
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High Power Switching Regulator Controller for DDR
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The internal circuit is composed of 2 stages inc
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via an RF or an infrared transmission medium upo
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The A-to-B enable (CEAB) input must be low in ord
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The mounting area was reduced by mak- ing the tw