xc2c128-7vqg100i DataSheet
DATASHEET
xc2c128-7vqg100i 描述
n Internal Start-up Bias Regulator n 3A Compound Main Gate Driver n Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis n Voltage Mode Control with Feed-Forward n Adjustable Dual Mode Over-Current Protection n Programmable Overlap or Deadtime between the Main and Active Clamp Outputs n Volt x Second Clamp n Programmable Soft-start n Leading Edge Blanking n Single Resistor Programmable Oscillator n Oscillator UP / DOWN Sync Capability n Precision 5V Reference n Thermal Shutdown
xc2c128-7vqg100i 特点
The functionally complete XC2C128-7VQG100I contains a fast-settling sample/hold amplifier, a subranging (two-pass) A/D converter, an internal reference, timing/control logic, and error-correction circuitry. Digital input and output levels are TTL. The XC2C128-7VQG100I only requires the rising edge of a start convert pulse to operate.
xc2c128-7vqg100i 应用
• HiPerFETTM technology - low RDSon - low gate charge for high frequency operation - unclamped inductive switching (UIS) capability - dv/dt ruggedness - fast intrinsic reverse diode • ISOPLUS i4-PACTM package - isolated back surface - low coupling capacity between pins and heatsink - enlarged creepage towards heatsink - application friendly pinout - low inductive current path - high reliability - industry standard outline - UL registered E 72873
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
17911
via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
4838
The BRT (Bias Resistor Transistor) contains
4726
The deserializer stays in lock until it cannot de
8877
Output, Pin 14, is suitable for controlling a pow
11204
IOAPIC clock output. (14.318 MHz) Poweredby VDDL
14634
Generates a Regulated Auxiliary Output in Isolated
14746
4.4 Conformance inspection. Conformance ins
11540
2. Intersil Pb-free plus anneal products employ s
14971
Parameter SK Clock Frequency SK High Time