XC2S100E-6FTG256I DataSheet
DATASHEET
XC2S100E-6FTG256I 描述
The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and con- trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as reg- istered mode.
XC2S100E-6FTG256I 特点
The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later. Program- mable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise.
XC2S100E-6FTG256I 应用
• PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh (15.6µs/row) • LVTTL-compatible inputs and outputs • Single +3.3V 0.3V power supply • Supports CAS latency of 1, 2, and 3
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