XC2S100-5PQG208I DataSheet
DATASHEET
XC2S100-5PQG208I 描述
2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL C 50) Vfk
XC2S100-5PQG208I 特点
The XC2S100-5PQG208I/XC2S100-5PQG208I high-voltage linear regulators operate from a +6.5V to +65V input voltage and deliver up to 150mA of output current. These devices consume only 60µA of quiescent current with no load and with- stand a -60V reverse-battery voltage at the input. The XC2S100-5PQG208I/XC2S100-5PQG208I include an active-low internal microprocessor (µP) reset circuit that asserts when the regulator output drops below the preset output voltage threshold by 7.5% or 12.5%, depending on the device selected. Both devices are available with a fixed +3.3V or +5V output. These devices are short- circuit protected and include thermal shutdown.
XC2S100-5PQG208I 应用
The XC2S100-5PQG208I/XC2S100-5PQG208I low-power, high-speed, serial- output, 12-bit, analog-to-digital converters (ADCs) oper- ate at up to 1.5Msps. These devices feature true-differen- tial inputs, offering better noise immunity, distortion improvements, and a wider dynamic range over single- ended inputs. A standard SPI™/QSPI™/MICROWIRE™ interface provides the clock necessary for conversion. These devices easily interface with standard digital signal processor (DSP) synchronous serial interfaces.
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
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Addresses and chip enables are registered at risin
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The XC5200 Field-Programmable Gate Array Family i
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Wiper position programming defaults to midscale a
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The CS5381 uses a 5th-order, multi-bit delta-sigma
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The mounting area was reduced by mak- ing the tw
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The A-to-B enable (CEAB) input must be low in ord
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via an RF or an infrared transmission medium upo
4950
Note 2: The maximum power dissipation is dictated
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The BRT (Bias Resistor Transistor) contains
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The deserializer stays in lock until it cannot de
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Output, Pin 14, is suitable for controlling a pow
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The challenge for an integrated clock-recovery cir
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The AC16543 are 16-bit registered transceivers t
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Byte Write Following the start signal from the ma
3755
Before the A/D digitizing the voice-band analog s
10503
In addition, the PCI interface can either be used