XC2S50E-6TQG144C DataSheet
DATASHEET
XC2S50E-6TQG144C 描述
Two N-channel MOSFETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. The gate terminals for these MOSFETS (VCC_DDC) should be connected to the supply rail (typically 3.3V) that sup- plies power to the transceivers of the DDC controller.
XC2S50E-6TQG144C 特点
The XC2S50E-6TQG144CA octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
XC2S50E-6TQG144C 应用
The Read operation of the EM39LV040 is controlled by CE# and OE#. Both have to be Low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for further details.
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描述
询价
10241
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Description plastic lead chip carrier; 44 leads