主页 >> 半导体&集成电路(IC) >> 可编程逻辑 IC - XC2S50E-6PQG208C

XC2S50E-6PQG208C

工厂型号: XC2S50E-6PQG208C
型号类别: 可编程逻辑 IC
厂商: XILINX
型号: XC2S50E-6PQG208C
批号:
数量: 14971
更新日期: 2011/09/20

我们的销售团队能用多国语言交流,给予您及时的反馈!

*我们在周一至周五给你提供24小时的咨询服务。
*我们会在您询价24小时之内给予您一个详尽的报价。
*我们提供免费代用产品服务。

描述

特点

应用

XC2S50E-6PQG208C 描述

      Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to DO in 3-state Write Cycle Time 5V, 25ºC

XC2S50E-6PQG208C 特点

    When a surface mount balun is mounted to a printed circuit board, the primary concerns are; insuring the RF pads of the device are in contact with the circuit traces of the PCB and insuring the ground plane of neither the component nor the PCB is in contact with the RF signal. As long as the geometry of the unit fits onto the layout of the circuit trace on the PCB, and the conditions of the previous paragraph are followed, the baluns performance is ensured. An example of how the PCB footprint could look is shown below. In specific designs, the transmission line widths need to be adjusted to the unique dielectric coefficients and thicknesses as well as varying pick and place equipment tolerances.

XC2S50E-6PQG208C 应用

    built reflector suitable for backlighting of display panels for optical coupling into light pipes uniform illumination of a diffuser screen in front of the custom built reflector solder leads with stand-off available taped on reel load dump resistant acc. to DIN 40839
询价
姓名 *: 除了和您交流有关我们公司的相关信息,我们不会把您的电子邮件用于其他任何目的, 同时,公司也不会向第三方提供或透漏您的信息。
公司名称 *:
联系电话 *:
电子邮箱 *:
型号 *:
数量 *:
内容 :
如果我们公司的库存数据库中没有您需要的元器件,请在备注栏输入型号、数量,我们会为您提供紧急物料搜寻服务查找。

相关型号

型号
数量
厂商
批号
描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
  The floating-point register file is made u
13848
Hardware Reset, active Low. Provides a hardware me
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
15491
Wiper position programming defaults to midscale a
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
4950
Note 2: The maximum power dissipation is dictated
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
3275
Continuous Drain Current, VGS @ 10V Continuous D
7426
Drive Up To 15 LSTTL Loads Low Power Consumption,
11466
High Power Switching Regulator Controller for DDR
7501
Two N-channel MOSFETs provide the level shifting
11877
  Typical represents the average reading at
10154
VBBOutput reference voltage-1.38-1.22VIBB = 0.4 m
8632
The ADV7183A has a 5-line, superadaptive, 2D comb