xc3s500e-4pqg208c DataSheet
DATASHEET
xc3s500e-4pqg208c 描述
The AC16543 are 16-bit registered transceivers that contain two sets of D-type latches for temporary storage of data flowing in either direction.They can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
xc3s500e-4pqg208c 特点
The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the XC3S500E-4PQG208C detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The XC3S500E-4PQG208C continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the XC3S500E-4PQG208C issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible).
xc3s500e-4pqg208c 应用
Besides the USB interface, the XC3S500E-4PQG208C contains a WEP/TKIP engine block, an AES engine block, a MAC Support Unit (MSU), a 802.11b baseband controller, two memory controllers and the ARM® subsystem consisting of an Interrupt Controller, two 32-bit timers, and an address decoder unit.
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