xc3s250e-4tqg144i DataSheet
DATASHEET
xc3s250e-4tqg144i 描述
3.1 KSO0~7 These pins are direct output from the 8051 Port1 and dedicated for key scan output. The pin inputss function is removed. Read 8051 Port1 is only read the data in the Port1 output register. These pins aress Pseudo open-drain structure.
xc3s250e-4tqg144i 特点
Output Capacitors (Optional) For applications with load transients (sudden changes in load current), regulator response will benefit from an external output capacitance. The recommended output capacitance of 100 µF will allow the module to meet its transient response specification (see product data sheet). For most applications, a high quality computer-grade aluminum electrolytic capacitor is adequate. These capaci- tors provide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable when ambient temperatures above 0 C. For operation below 0 C tantalum, ceramic or Os-Con type capacitors are recommended. When using one or more non-ceramic capacitors, the calculated equiva- lent ESR should be no lower than 4 mΩ (7 mΩ using the manufacturers maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are identified in Table 1-1.
xc3s250e-4tqg144i 应用
Software Data Protection (SDP) The SST39VF160Q/VF160 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program opera- tion requires the inclusion of the three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte sequence. The SST39VF160Q/VF160 device is shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid com- mands will abort the device to read mode within TRC. The contents of DQ15-DQ8 are Dont Care during any SDP command sequence.
相关型号
型号
数量
厂商
批号
描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
5208
A high on the MASTER RESET (MR) sets all the cont
14048
Addresses and chip enables are registered at risin
16717
The XC5200 Field-Programmable Gate Array Family i
17695
The CS5381 uses a 5th-order, multi-bit delta-sigma
8886
The mounting area was reduced by mak- ing the tw
13759
The A-to-B enable (CEAB) input must be low in ord
8877
Output, Pin 14, is suitable for controlling a pow
3499
The challenge for an integrated clock-recovery cir
3275
Continuous Drain Current, VGS @ 10V Continuous D
7426
Drive Up To 15 LSTTL Loads Low Power Consumption,
11466
High Power Switching Regulator Controller for DDR
10817
The internal circuit is composed of 2 stages inc
18287
The Edge646 driver supports three distinct program
19657
• True dual-ported memory cells which allow
11091
n Internal Start-up Bias Regulator n 3A Compound
11204
IOAPIC clock output. (14.318 MHz) Poweredby VDDL
14634
Generates a Regulated Auxiliary Output in Isolated
14746
4.4 Conformance inspection. Conformance ins
11540
2. Intersil Pb-free plus anneal products employ s