XCS20-3TQ144C DataSheet
DATASHEET
XCS20-3TQ144C 描述
IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powered by VDDL (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CLK_STOP#. Freerunning IOAPIC clock output. Not affected by the CLK_STOP# (14.31818 MHz) Powered by VDDL
XCS20-3TQ144C 特点
power consuming, high-precision LCD panel display can be assembled using the XCS20-3TQ144C. In the segment mode, the data input is selected 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.
XCS20-3TQ144C 应用
The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con- trollers, etc.
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描述
询价
10241
11+
PARAMETER Reference Voltage Section Fb Voltage
13752
11+
The floating-point register file is made u
7372
pin signalised an interrupt (logic 0). However, if
14634
Generates a Regulated Auxiliary Output in Isolated
14746
4.4 Conformance inspection. Conformance ins
11540
2. Intersil Pb-free plus anneal products employ s
14971
Parameter SK Clock Frequency SK High Time
7501
Two N-channel MOSFETs provide the level shifting