TPS60403DBVR DataSheet
DATASHEET
TPS60403DBVR 描述
Information at the D input is transferred to the Q, Q outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q outputs to a logic 1.
TPS60403DBVR 特点
3 port trunking groups, one for the 2 Gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group Load sharing among trunked ports can be based on source MAC and/or destination MAC. The Gigabit trunking group has one more option, based on source port Port Mirroring to any two ports of 0-23 in managed mode or to a dedicated mirroring port or port 23 in unmanaged mode Full set of LED signals provided by a serial interface, or 6 LED signals dedicated to Gigabit port status only (without serial interface) Built-in MIB statistics counters Recognizes Simple Bandwidth Management (SBM) and Resource Reservation Protocol (RSVP) packets and forwards to CPU Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports Built-in reset logic triggered by system malfunction Built-in self test for internal and external SRAM I2C EEPROM for configuration 553 BGA package
TPS60403DBVR 应用
Technical/Catalog InformationTPS60403DBVRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Type
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9113
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