TPS5430DDAR DataSheet
DATASHEET
TPS5430DDAR 描述
ADC reference voltage that sets the maximum input signal level, setting the size of the least significant bit (LSB) in the analog to digital conversion process. ADC bias. ADC reference used for the calibration operation. Slave mode input signal. Active low pulse to reset row and column counters, providing frame synchronization. Low duration should be at least two-clock cycles wide. An input that is held LOW also sets the sensor in LOW, per standby mode, until it is released. Signal is pulled up on-chip. The user should ground this pin. Offset that may be needed for very short exposure conditions. Bias setting voltage for the ADC operating current. Serial port data.
TPS5430DDAR 特点
CD4510BMS Presettable BCD Up/Down Counter and the TPS5430DDAR Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ETPS5430DDARABLE line. The CD4510BMS will count out of non-BCD counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode.
TPS5430DDAR 应用
Technical/Catalog InformationTPS5430DDARVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Type