TPA6111A2DGNR DataSheet
DATASHEET
TPA6111A2DGNR 描述
Note 2: All input and/or output pins shall not exceed VCC + 0.5V and shall not exceed the absolute maximum rating at any time, including power-up and power-down. This prevents the ESD structure from being damaged due to excessive currents flowing from the input and/or output pins to QV CC and VCC. There is a diode between each input and/or output to VCC which is forward biased when incorrect sequencing is applied. LI and Bn pins do not have power sequencing requirements with re- spect to V CC and QVCC.
TPA6111A2DGNR 特点
† The PW package is available taped and reeled. Add R suffix to device type (e.g. TPA6111A2DGNRPWR) to order quantities of 2,000 devices per reel. Bulk quantities are 70 units per tube. ‡ The TSSOP-20 (PW) package uses Pb-free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255C to 260C peak reflow temperature and compatible with either lead free or Sn/Pb soldering operations.
TPA6111A2DGNR 应用
Technical/Catalog InformationTPA6111A2DGNRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Package / Case
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