MJE340G DataSheet
DATASHEET
MJE340G 描述
When executing a jump instruction, conditional skip ex- ecution, loading to the PCL register, performing a sub- routine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from inter- rupts, the PC manipulates the program transfer by load- ing the address corresponding to each instruction.
MJE340G 特点
The MJE340G and MJE340G are low-power BiMOS devices containing three independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the MJE340G and MJE340G are similar to those of the MJE340G75C188 quadruple driver and MJE340G75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/µs, and the receivers have filters that reject input noise pulses shorter than 1 µs. Both these features eliminate the need for external components.
MJE340G 应用
When at least one of the reset outputs is not asserted, a pushbut- ton initiated reset signal can be issued by holding PBRST LOW for at least 2ms. When PBRST is held LOW, both resets become active and remain active for approximately 350ms after PBRST returns HIGH. See Figure 3 and Figure 4.