LMV331IDCKR DataSheet
DATASHEET
LMV331IDCKR 描述
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and
LMV331IDCKR 特点
Figures 3 and 4, starting at time T4, depict the transitions from sleep states to the S0 wake state. Figure 3 shows the transition of the LMV331IDCKR/B from the S4/S5 state to the S0 state. Figure 4 shows how the LMV331IDCKR/B will transition from the S3 sleep state into S0 state. Figure 3 also shows how the LMV331IDCKRA transitions from either S3 or S4/S5 in the S0 state. For all transitions, T4 depicts the system transition into the S0 state. Here, the ATX supplies are enabled and begin to ramp up. At time T5, the 12VATX rail has exceeded the POR threshold for the LMV331IDCKR/B and LMV331IDCKRA. Three soft start periods after time T5, at time T6, three events occur
LMV331IDCKR 应用
Technical/Catalog InformationLMV331IDCKRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Type