HCPL-6531 DataSheet
DATASHEET
HCPL-6531 描述
4. This parameter is sampled and not 100% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE transition LOW. 8. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9. Read Cycle Time is measured from the last valid address to the first transitioning address.
HCPL-6531 特点
n Fully integrated 10 Mbps Ethernet transceiver Comprehensive Auto-Negotiation implementation IEEE 802.3u-compliant MII Full-duplex operation supported on the MII port with independent Transmit (TX) and Receive (RX) channels Optimized for 10BASE-T applications n Compliant with HomePNA specification 1.1 n General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) n Extensive programmable internal/external loopback capabilities n Extensive LED status support n IEEE 1149.1-compliant JTAG Boundary Scan test access port interface n Very low power consumption
HCPL-6531 应用
The HCPL-6531 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The HCPL-6531 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the de- sign or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the intercon- nects between the Serializer and Deserializer to be verified at-speed.