FX6-100S-0.8SV2(71) DataSheet
DATASHEET
FX6-100S-0.8SV2(71) 描述
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.
FX6-100S-0.8SV2(71) 特点
Functional Description The FX6-100S-0.8SV2(71) is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL compatible signals. Each of the four output banks of two, three, four and six differential clock output pairs can be independently configured to distribute the input frequency or 2 of the input frequency. The FSELA, FSELB, FSELC, FSELD and CLK_SEL are asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the the 2 outputs. For the functionality of the MR control input, see Figure 5. , Functional Diagram, on page 7. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The FX6-100S-0.8SV2(71) can be operated from a single 3.3V or 2.5V supply. As most other ECL compatible devices, the FX6-100S-0.8SV2(71) supports positive (PECL) and negative (ECL) supplies. The FX6-100S-0.8SV2(71) is pin and function compatible to the MC100EP222.
FX6-100S-0.8SV2(71) 应用
Technical/Catalog InformationFX6-100S-0.8SV2(71)VendorHirose Electric Co LtdCategoryConnectors Connector Type