FH12-30S-0.5SH(55) DataSheet
DATASHEET
FH12-30S-0.5SH(55) 描述
Serial Clock (SCL). This input signal is used to strobe all data in and out of the device. In applica- tions where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchro- nization is not employed, and so the pull-up resis- tor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA). This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-ORed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Se-
FH12-30S-0.5SH(55) 特点
The device is available with an access time of 70 or 85 ns and is offered in a 73-ball FBGA package. Standard control pinschip enable (CE#f), write enable (WE#), and output enable (OE#)control normal read and write operations, and avoid bus contention issues.
FH12-30S-0.5SH(55) 应用
Technical/Catalog InformationFH12-30S-0.5SH(55)VendorHirose Electric Co Ltd (VA)CategoryConnectors Pitch