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MSP430F413IPMR

工厂型号: MSP430F413IPMR
型号类别: 嵌入式处理器(MCU, MPU, DSP, DSC, SoC)
厂商: TI
型号: MSP430F413IPMR
批号: 11+
数量: 4392
更新日期: 2011/09/08

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描述

特点

应用

MSP430F413IPMR 描述

    Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0CP0.2 are open drain. Port 0.0CP0.2 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. P0.3CP0.4 are bidirectional I/O port pins with internal pull-ups. These pins are driven low if the port register bit is written with a 0. The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs.

MSP430F413IPMR 特点

    Data Transfer After all address information has been transmitted, data transfer between the bus master and the MSP430F413IPMR can begin. For a read operation the device will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded. For a write operation, the MSP430F413IPMR will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MMSP430F413IPMRB (most significant bit) first.

MSP430F413IPMR 应用

    Technical/Catalog InformationMSP430F413IPMRVendorTexas InstrumentsCategoryIntegrated Circuits (ICs) Program Memory Size
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