MSP430F169IPMR DataSheet
DATASHEET
MSP430F169IPMR 描述
MSP430F169IPMR 特点
MPI CONTROL MODE In MPI mode, the internal configuration registers (local/global), the SLIC signaling interface and the Coefficient-RAM, FSK-RAM of the MSP430F169IPMR are programmed by microprocessor via the serial control interface, which consists of four lines (pins): CCLK, CS, CI and CO. All the commands and data transmitted or received are aligned in byte (8 bits). CCLK is the Serial Control Interface Clock, it can be up to 8.192 MHz; CS is the Chip Select pin, a low level on it enables the serial control interface; CI and CO are the serial control interface data input and output, carrying the control commands and data bytes to/from the MSP430F169IPMR. The data transfer is synchronized to the CCLK input. The contents of CI is latched on the rising edges of CCLK, while CO changes on the falling edges of CCLK. When finishing a read or write command, the CLCK must last at least one cycle after the CS is set high. During the execution of commands that are followed by output data (read commands), the device will not accept any new commands from CI. The data transfer sequence can be interrupted by setting CS high. See Figure 1 and Figure 2. CCLK is the only reference of CI and CO pins. Its duty and frequency may not necessarily be standard.
MSP430F169IPMR 应用
Technical/Catalog InformationMSP430F169IPMRVendorTexas Instruments (VA)CategoryIntegrated Circuits (ICs) Program Memory Size